NXP Semiconductors /LPC18xx /USB0 /USBCMD_H

Run/Stop

0 (HALT): When this bit is set to 0, the Host Controller completes the current transaction on the USB and then halts. The HC Halted bit in the status register indicates when the Host Controller has finished the transaction and has entered the stopped state. Software should not write a one to this field unless the host controller is in the Halted state (i.e. HCHalted in the USBSTS register is a one).

1 (PROCEED): When set to a 1, the Host Controller proceeds with the execution of the schedule. The Host Controller continues execution as long as this bit is set to a one.

Controller reset. Software uses this bit to reset the controller. This bit is set to zero by the Host/Device Controller when the reset process is complete. Software cannot terminate the reset process early by writing a zero to this register.

0 (RESETCOMPLETE): This bit is set to zero by hardware when the reset process is complete.

1 (RESET): When software writes a one to this bit, the Host Controller resets its internal pipelines, timers, counters, state machines etc. to their initial value. Any transaction currently in progress on USB is immediately terminated. A USB reset is not driven on downstream ports. Software should not set this bit to a one when the HCHalted bit in the USBSTS register is a zero. Attempting to reset an actively running host controller will result in undefined behavior.

Bit 0 of the Frame List Size bits. See Table 220. This field specifies the size of the frame list that controls which bits in the Frame Index Register should be used for the Frame List Current index. Note that this field is made up from USBCMD bits 15, 3, and 2.

Bit 1 of the Frame List Size bits. See Table 220.

This bit controls whether the host controller skips processing the periodic schedule.

0 (DO_NOT_PROCESS_THE_P): Do not process the periodic schedule.

1 (USE_THE_PERIODICLIST): Use the PERIODICLISTBASE register to access the periodic schedule.

This bit controls whether the host controller skips processing the asynchronous schedule.

0 (DO_NOT_PROCESS_THE_A): Do not process the asynchronous schedule.

1 (USE_THE_ASYNCLISTADD): Use the ASYNCLISTADDR to access the asynchronous schedule.

This bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances asynchronous schedule.

0 (THE_HOST_CONTROLLER_): The host controller sets this bit to zero after it has set the Interrupt on Sync Advance status bit in the USBSTS register to one.

1 (SOFTWARE_MUST_WRITE_): Software must write a 1 to this bit to ring the doorbell. When the host controller has evicted all appropriate cached schedule states, it sets the Interrupt on Async Advance status bit in the USBSTS register. If the Interrupt on Sync Advance Enable bit in the USBINTR register is one, then the host controller will assert an interrupt at the next interrupt threshold. Software should not write a one to this bit when the asynchronous schedule is inactive. Doing so will yield undefined results.

Reserved

Asynchronous schedule park mode Contains a count of the number of successive transactions the host controller is allowed to execute from a high-speed queue head on the Asynchronous schedule before continuing traversal of the Asynchronous schedule. Valid values are 0x1 to 0x3. Software must not write 00 to this bit when Park Mode Enable is one as this will result in undefined behavior.

Reserved.

Asynchronous Schedule Park Mode Enable

0 (PARK_MODE_IS_DISABLE): Park mode is disabled.

1 (PARK_MODE_IS_ENABLED): Park mode is enabled.

Reserved.

Not used in Host mode.

Reserved.

Bit 2 of the Frame List Size bits. See Table 220.

Interrupt threshold control. The system software uses this field to set the maximum rate at which the host/device controller will issue interrupts. ITC contains the maximum interrupt interval measured in micro-frames. Valid values are shown below. All other values are reserved. 0x0 = Immediate (no threshold) 0x1 = 1 micro frame. 0x2 = 2 micro frames. 0x8 = 8 micro frames. 0x10 = 16 micro frames. 0x20 = 32 micro frames. 0x40 = 64 micro frames.

Reserved